Verilog - range handling with named values -

i have assigned names numbers using:

`define add 0 `define sub 1 `define lsf 2 `define rsf 3 `define , 4 `define or 5 

i'd handle in case block such code apply more 1 option. in c can done using:

switch (x){  case add: case sub: case lsf: case rsf: case and: case or:     printf ("handling");     break; } 

is there way achieve in verilog? thanks!

yup, commas!

case (x) add, sub, lsf, rsf, and, or: begin     $display("handling multiple cases");     // no need breaks end mult: begin     $display("handle single case"); end default: begin     $display("do other cases"); end endcase