case - How to "sample" a value in VHDL? -

so have modulo counter going 1->15, looping around in seperate entity. to, in case statement depending on outputs, sample value on rising_edge of clock, once, otherwise value changing. there way this? assign signal , have stay static? i've posted code hope demonstrate trying bit better.

process(all)        begin --sensitivity list?       if(reset)           playercards <= "0000000000000000";           dealercards <= "0000000000000000";       elsif rising_edge(clock)         case? deal & dealto & dealtocardslot           when "1100" =>             playercards(3 downto 0) <= singlecard;                     playercards(15 downto 4) <= (others => '0');           when "1101" =>             playercards(7 downto 4) <= singlecard;                     playercards(15 downto 8) <= (others => '0');           when "1110" =>             playercards(11 downto 8) <= singlecard;                     playercards(15 downto 12) <= (others => '0');           when "1111" =>             playercards(15 downto 12) <= singlecard;           when "1000" =>             dealercards(3 downto 0)   <= singlecard; --dcard1             dealercards( 15 downto 4) <= (others => '0');           when "1001" =>             dealercards(7 downto 4)   <= singlecard; --dcard2             dealercards( 15 downto 8) <= (others => '0');           when "1010" =>             dealercards(11 downto 8)  <= singlecard; --dcard3             dealercards( 15 downto 12) <= (others => '0');           when "1011" =>             dealercards(15 downto 12) <= singlecard; --dcard4           when "0--0" => null;                       --do nothing when in win/end           when others => --this covers start case --sets cards 0             playercards <= "0000000000000000";             dealercards <= "0000000000000000";          end case?;       end if;   end process; 

here have singlecard being linked output of counter, increments every clock edge. case statement happen update value of playercards once, , stop. help.

your requirement can stated : process can in 2 states - sampling, or not sampling, , transition not sampling when sample.

so can state variable, in case can boolean - turns process state machine. other answer says, can use signal here instead of variable, breaks encapsulation, making processes internal workings visible.

some people insist separate out state machine 2 (or 3) processes, think single process form lot smaller , easier understand.

   process(reset,clock) -- original sens list incorrect clocked process    variable sampling : boolean;    begin        if(reset)           sampling <= true;           -- other reset actions       elsif rising_edge(clock)          if sampling   -- add conditions here, or it'll sample on first clock.             sampling := false;             case ... -- sampling process , program logic             end case;          else             -- if need turn sampling on, set "sampling" here          end if;       end if;    end process;