VHDL audio sample volume control -


i searching lot problem, cant find usefull... problem is, im making echo efect on fpga chip.. have prepared, bram delay, input, output delay, can't find out, how change volume of output coming input, mix them , send them again bram.. becouse when conect output input, makes cycle of bram infinite, need change volume of output, coming input, half of volume.. read can achived shifting sample right, makes lot of noise on sample..

im using 16 bit samples

so i'm asking ideas how control volume of sample, else have prepared..

so find out problem.. shifting sample vector right, made "0" & sample(15 downto 1) signed, had copy msb instead of adding plain "0".. answer is

sample(15) & sample(15 downto 1)

this make sample half of original volume.. sample * 0,5


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