vhdl - Can I access a constant inside a instantiated entity from outside? -

i have vhdl entity generic parameter list. architecture entity calculates several constants, needed create intended functionality.

is possible access 1 of these constants outside?

example 1:
let's there fifo decides based on depth , outreg best implementation (register based, srl based or blockram based). depending on minimum delay through fifo can vary 1 2 cycles.

example 2:
consider same fifo cross clock compatible. min delay depends on choosen sync circuits , frequency difference.

example 3:
division entity needs n cycles calculate a div b. n depends on bits, radix, outreg, is_signed, ...

further let's each entity has min_delay constant of type natural of interest other instances.

e.g. instantiating entity needs know how long must @ least wait result.

i can think of 2 solutions, think neither nice one.

solution 1:
store algorithmn computation in package it's globally accessable. against encapsulation principle :). outside world needs know delay value not algorithmn.

solution 2:
use valid bit. that's solution in dynamic, adaptive or pipelined systems, bit can not used @ synthesis time further choices or optimizations.

possible solution 3:
vhdl has ability define new attributes, can accessed?

example entity: alu_div:

constant min_delay : natural := bits / log2(radix) + 2; attribute delay   : natural; attribute delay of alu_div : entity min_delay; 

example top:

mydiv : entity work.alu_div    generic map (....)    port map (....);  blk : block   constant : natural := mydiv'delay; begin   .... end block; 

new: possible solution 4:
found se question, jim lewis noted hierarchical references should work constants.
alias my_delay <<constant mydiv.delay : natural >>;
get internal signals of vhdl design in ncvhdl (alternative modelsim's signal spy)

agree useful information implementation details entity, though breaks encapsulation principle, white box verification can great help.

tried use entity attribute based on entity like:

entity alu_div   generic(     bits  : positive;     radix : positive);    port(     ...);   constant min_delay : natural := bits / log2(radix) + 2;   attribute delay   : natural;   attribute delay of alu_div : entity min_delay; end entity; 

but module alu_div instantiated not able access using e.g. alu_div_0'delay, since modelsim gives error:

no attribute specification designator "delay" decorates label "alu_div_0".

one method useful white box verification, verification depends on implementation, make output port information implementation, like:

entity alu_div   ...   port(     ...     delay_o : out natural);   ... end entity;  architecture syn of alu_div begin   delay_o <= min_delay;   ... 

it won't true constant, since simulation need delta cycle before getting value, may sufficient solution in many cases.